1. Field of the Invention
The present invention relates to an analog/digital (which will be referred also to as "A/D") converter for converting an analog signal to a digital signal.
2. Description of the Background Art
FIG. 13 shows a structure of a pipeline A/D converter in the prior art. As shown in FIG. 13, the pipeline A/D converter includes a sample-hold circuit 2 for sampling and holding an input voltage, A/D sub-converters 4, 11, 13 and 15 connected in series to sample-hold circuit 2, and a digital circuit 1 connected to each of A/D sub-converters 4, 11, 13 and 15.
Each of A/D sub-converters 4, 11 and 13 includes a flash A/D converter 5 which converts an input analog voltage into a digital signal for outputting the same to digital circuit 1, a digital/analog (which will be referred to also as "D/A") converter 7 which outputs an analog voltage corresponding to the input digital signal, and a subtracter 9 which subtracts the output voltage of D/A converter 7 from the analog voltage supplied to the A/D sub-converter and outputs the result of subtraction after amplifying the same.
A/D sub-converter 15 at the final stage includes a flash A/D converter 16.
FIG. 14 shows specific structures of sample-hold circuit 2 and A/D sub-converter 4 shown in FIG. 13. As shown in FIG. 14, sample-hold circuit 2 includes switches S0, S0A and S0B, a capacitor C0 and an amplifier 3. A/D sub-converter 4 includes a switch S1, a flash A/D converter 5, a D/A converter 7, capacitors C1A and C1B, and an amplifier 8.
Switches S0 and S0A are turned on in response to activation of signal .phi., and switches S0B and S1 are turned on in response to activation of a signal /.phi..
An operation of the circuit shown in FIG. 14 will be described below with reference to timing charts of FIGS. 15A and 15B.
Signal .phi. periodically attains a high level (H-level) and a low level (L-level) as shown in FIG. 15B.
In a sample period during which signal .phi. is at H-level, switches S0 and S0A are turned on, and a voltage VB is applied to an input terminal of amplifier 3, so that an output offset voltage shown by solid line in FIG. 15A is supplied to an output node NO of amplifier 3. This output offset voltage is applied to capacitor C1B.
In this sample period, voltages VIN and VB are applied to input and output terminals of capacitor C0, respectively, and voltage VIN is sampled.
In the hold period during which signal .phi. is at L-level, switches S0 and S0A are off, switch S0B is on, and capacitor C0 is supplied on its input terminal with voltage VB, so that the operation is in such a hold state that the amplifier 3 is supplied on its input terminal with a voltage Vx (=-VIN+2VB). In this state, amplifier 3 applies to output node N0 a signal voltage including an output offset voltage V.sub.offset as indicated by solid line in FIG. 15A.
As described above and represented by solid line in FIG. 15A, amplifier 3 alternately outputs the signal voltage containing the output offset voltage and the signal voltage containing output offset voltage V.sub.offset, which are applied to capacitor C1B. Thereby, capacitor C1B subtracts output offset voltage V.sub.offset from the signal voltage, and an offset-canceled and therefore true signal voltage is obtained.
FIG. 16 shows a structure of a voltage comparator included in flash A/D converter 5. As shown in FIG. 16, this voltage comparator includes two input terminals 18, capacitors C2A, C2B and C, switches S2 and S3, amplifiers 17 and 19, and a latch circuit 21.
Here, one of input terminals 18 is connected to sample-hold circuit 2 and output node N0, and the other is supplied with a reference voltage for comparison.
Similarly to amplifier 3 included in the aforementioned sample-hold circuit 2, amplifiers 17 and 19 included in this voltage comparator alternately issue output offset voltages and voltages representing results of comparison, and capacitor C performs offset canceling.
Sample/hold circuit 2 and subtracter 9 included in the pipeline A/D converter in the prior art shown in FIG. 13 produce an offset voltage V.sub.offset in the sample period based on an initial value which is a value of a voltage amplified in the last hold period. Therefore, a certain time is unpreferably required before output offset voltage V.sub.offset is produced.
Likewise, the voltage comparator in the prior art produces an output offset voltage in the sample period based on an initial value which is a value of a voltage amplified in the last hold period and representing the result of comparison.